While electronic devices are becoming more and more sophisticated, any minute error can have unexpected influence on the operations of these devices. Consequently, increasingly heightened requirements are being imposed on accuracy of electronic devices. FIG. 1 is a circuit diagram of a conventional current regulator 10, in which a current source 12 is connected between a voltage source VDD and a drain of a transistor 18 to provide a reference current IREF, a single-ended operational amplifier 16 has a non-inverting input connected to the drain of the transistor 18 and an output connected to a gate of the transistor 18 to establish a negative feedback path therewith, and a transistor 19 has a drain connected to an inverting input of the single-ended operational amplifier 16 and a gate connected to the output of the single-ended operational amplifier 16 to establish a positive feedback path therewith, and mirrors the current in the transistor 18 to generate a load current ILED for a light-emitting diode (LED) 14. In FIG. 1, the voltage source VOS at the inverting input of the single-ended operational amplifier. 16 represents the offset effect of the single-ended operational amplifier 16. FIG. 2 is a diagram to illustrate the I-V curve of the current regulator 10 shown in FIG. 1. Ideally, the single-ended operational amplifier 16 has no offset and the relationship between the load current ILED and the supply voltage VDD is piecewise linear as shown by the curve 22. In this case, because of the constant forward voltage of the LED 14, the voltage at the drain of the transistor 19 decreases with the decrease of the supply voltage VDD. Due to the virtual short between the inputs of the single-ended operational amplifier 16, the voltages at the drains of the transistors 18 and 19 will be equal to each other, and thus the load current ILED will remain constant, unless the supply voltage VDD decreases beyond a threshold Vth. After this point of VDD=Vth, the single-ended operational amplifier 16 can no longer keep the voltages at the drains of the transistors 18 and 19 equal to each other, and the load current ILED will decrease with the decreasing supply voltage VDD. However, the single-ended operational amplifier 16 may have offset due to unmatched components thereof. If the offset voltage VOS is positive, the load current ILED will have a peak, as shown by the curve 20 of FIG. 2. On the contrary, if the offset voltage VOS is negative, the load current ILED will fall down in advance before the supply voltage VDD becomes lower than the threshold Vth, as shown by the curve 24 of FIG. 2.
FIG. 3 is a circuit diagram of another conventional current regulator 30, in which a current source 32 is connected between a voltage source VDD and a resistor REF to provide a reference current IREF, and a single-ended operational amplifier 36 has an inverting input connected to the node A between the current source 32 and the resistor REF, an output connected to a gate of a transistor 38, and a non-inverting input connected to the node B between a source of the transistor 38 and a resistor RSET. Because of the virtual short between the inputs of the single-ended operational amplifier 36, the voltage at the node B will be equal to that at the node A, and this voltage VB will determine a load current ILED for a LED 34 serially connected to the transistor 38 and resistor RSET. In FIG. 3, the voltage source VOS at the inverting input of the single-ended operational amplifier 36 represents the offset effect of the single-ended operational amplifier 36, and FIG. 4 is a diagram to illustrate the relationship between the load current ILED and the reference current IREF in the current regulator 30 due to the offset voltage VOS. Ideally, the single-ended operational amplifier 36 has no offset and the curve representing the relationship between the load current ILED and the reference current IREF is a straight line passing through the origin, as shown by the curve 42 of FIG. 4. If the single-ended operational amplifier 36 has a positive offset, the relationship curve of the load current ILED and the reference current IREF will shift upward, as shown by the curve 40 of FIG. 4; while if the single-ended operational amplifier 36 has a negative offset, the relationship curve of the load current ILED and the reference current IREF will shift downward, as shown by the curve 44 of FIG. 4.
As shown in FIGS. 2 and 4, the offset voltage VOS of the single-ended operational amplifiers 16 and 36 may result in error in the load current ILED provided by the current regulators 10 and 30, so it is necessary to cancel the offset VOS of the single-ended operational amplifiers 16 and 36 in order to provide accurate current ILED by the current regulators 10 and 30. For offset cancellation of operational amplifiers, there have been proposed many arts, for example, “Design of Analog CMOS Integrated Circuits”, Pages 474-476, McGraw-Hill International Publications, 2001, and U.S. Pat. Nos. 6,194,962, 5,061,900, 6,459,335, 6,573,783 and 5,550,512.
FIGS. 5 and 6 show two states of a conventional operational amplifier 50 with offset cancellation mechanism, respectively, in which FIG. 5 is the configuration of the operational amplifier 50 in normal operation mode, and FIG. 6 is the configuration of the operational amplifier 50 in offset cancellation mode. The operational amplifier 50 includes transconductance amplifiers 52 and 56 having their outputs 5206, 5208 and 5606, 5608 connected together respectively, an output stage 54 having inputs 5402 and 5404 respectively connected to the outputs 5206, 5606 and 5208, 5608, and outputs 5406 and 5408 respectively connected to outputs 5006 and 5008 of the operational amplifier 50, switches S1 and S2 connected between two inputs 5202 and 5204 of the transconductance amplifier 52 and a voltage source VCM, respectively, switches S3 and S4 connected between inputs 5002 and 5004 of the operational amplifier 50 and the inputs 5202 and 5204 of the transconductance amplifier 52, respectively, switches S5 and S6 connected between the outputs 5406 and 5408 of the output stage 54 and inputs 5602 and 5604 of the transconductance amplifier 56, respectively, and capacitors C1 and C2 connected between the inputs 5602 and 5604 of the transconductance amplifier 56 and a ground terminal GND.
FIG. 7 shows the circuit of the operational amplifier 50 in detail. In the offset cancellation mode, as shown in FIGS. 6 and 7, the switches S1, S2, S5 and S6 are on and the switches S3 and S4 are off. Therefore, the inputs 5202 and 5204 of the transconductance amplifier 52 are supplied with the voltage VCM, and the inputs 5602 and 5604 of the transconductance amplifier 56 are connected to the outputs 5406 and 5408 of the output stage 54 respectively. The transconductance amplifier 52 includes a differential input pair that establishes currents I1 and I2 in the outputs 5206 and 5208 according to the voltages at the inputs 5202 and 5204. In the output stage 54, current sources 5410 and 5412 are connected to the inputs 5402 and 5404 of the output stage 54 respectively, to source equal currents I3 and I4 that are partially sink by the transconductance amplifier 52 by the currents I1 and I2 so as to leave currents I5 and I6. However, even the inputs 5202 and 5204 of the transconductance amplifier 52 are connected to the same voltage source VCM, due to the offset voltage VOS in the input 5202 of the transconductance amplifier 52, the currents I1 and I2 are actually unequal to each other and consequently, the currents I5 and I6 are unequal to each other. As a result, the voltages at the outputs 5406 and 5408 of the output stage 54 are unequal to each other. The capacitors C1 and C2 store the voltages at the outputs 5406 and 5408 of the output stage 54 respectively, and the transconductance amplifier 56 includes a differential input pair that sinks currents I7 and I8 from the inputs 5402 and 5404 of the output stage 54 according to the voltages at the outputs 5406 and 5408 of the output stage 54, so as to make the currents I5 and I6 equal to each other. Then, the operational amplifier 50 is switched to the normal operation mode, where the switches S3 and S4 are on and the switches S1, S2, S5 and S6 are off, as shown in FIG. 5. In this state, the voltages stored in the capacitors C1 and C2 will make the transconductance amplifier 56 sinking the currents I7 and I8 to cancel the effect caused by the offset voltage VOS. However, the operational amplifier 50 is a two-ended operational amplifier, so it is inapplicable to the current regulators 10 and 30 shown in FIGS. 1 and 2 respectively.
Therefore, it is desired a single-ended operational amplifier which is offset cancelled.